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1 for more information www.linear.com/ltc7812 typical application description low i q , 38v synchronous boost+buck controller the lt c ? 7812 is a high performance synchronous boost+buck dc/dc switching regulator controller that drives all n-channel power mosfet stages. it contains independent step- up ( boost) and step- down ( buck) control - lers that can regulate two separate outputs or be cascaded to regulate an output voltage from an input voltage that can be above, below or equal to the output voltage. the ltc7812 operates from a wide 4.5v to 38v input supply range. when biased from the output of the boost regulator, the ltc7812 can operate from an input supply as low as 2.5v after start-up. the 33a no-load quiescent current extends operating run time in battery-powered systems. unlike conventional buck- boost regulators, the ltc7812 s cascaded boost+ buck solution has continuous, non- pulsating, input and output currents, substantially reducing voltage ripple and emi. the ltc7812 has independent feedback and compensation points for the boost and buck regulation loops, enabling a fast output transient response that can be easily optimized externally. l, lt , lt c , lt m , burst mode, opti-loop and module are registered trademarks and no r sense is a trademark of analog devices, inc. all other trademarks are the property of their respective owners. features applications n synchronous boost and buck controllers n when cascaded, allows v in above, below or equal to regulated v out n output remains in regulation through input dips (e.g., cold crank) down to 2.5v n wide bias input voltage range: 4.5v to 38v n low input and output ripple n low emi n fast output transient response n high light load efficiency n low operating i q : 33a (both channels on) n low operating i q : 28a (buck channel on) n r sense or lossless dcr current sensing n buck output voltage range: 0.8v v out 24v n boost output voltage up to 60v n phase-lockable frequency (75khz to 850khz) n small 32-pin 5mm 5mm qfn package n automotive and industrial power systems n high power battery operated systems wide input range to 12v/8a low i q , cascaded boost+buck regulator + + + ltc7812 7812fc 2m 1h 3m 4.7h 499k 35.7k freq intv cc v fb2 run1 v in 5v to 38v down to 2.5v after start-up 15k 4.7nf 0.01f 0.1f 100pf extv cc ss2 i th1 sgnd 7812 ta01a 33f run2 i th2 sense2 ? sense2 + v fb1 pgnd v bias tg2 sw2 boost2 6.8f bg2 bg1 boost1 sw1 tg1 sense1 + sense1 ? pllin/mode track/ss1 ltc7812 0.1f 1.86k 6.8nf 820pf 6.8f 47f 22f 33f 499k 46.4k * when v in < 8v, maximum load current available is reduced 0.1f ** v mid = 14v when v in < 14v v mid follows v in when v in > 14v 4.7f v out 12v 8a* v mid , 14v**
2 for more information www.linear.com/ltc7812 absolute maximum ratings bias input supply voltage ( v bias ) .............. C 0.3 v to 40 v buck top side driver voltage ( boost 1) .... C 0.3 v to 46 v boost top side driver voltage ( boost 2) .... C 0.3 v to 76 v buck switch voltage ( sw 1) ......................... C 5 v to 40 v boost switch voltage ( sw 2) ........................ C 5 v to 70 v intv cc , ( boost 1C sw 1), ( boost 2 C sw 2) ...................................... C 0.3 v to 6 v run 1, run 2 ............................................... C 0.3 v to 8 v maximum current sourced into pin from source >8 v .............................................. 100 a bg 1, bg 2, tg 1, tg 2 ........................................... ( note 8) sense 1 + , sense 1 C voltages ...................... C 0.3 v to 28 v sense 2 + , sense 2 C voltages ..................... C 0.3 v to 40 v freq voltage ........................................ C 0.3 v to intv cc extv cc ...................................................... C 0.3 v to 14 v i th 1 , i th 2 , v fb 1 , v fb 2 , voltages .................... C 0.3 v to 6 v pllin / mode , pgood 1, ov 2 voltages ........ C 0.3 v to 6 v track / ss 1, ss 2 voltages .......................... C 0.3 v to 6 v operating junction temperature range ( notes 2, 3) ltc 7812 e , ltc 7812 i .......................... C 40 c to 125 c ltc 7812 h .......................................... C40 c to 150 c storage temperature range .............. C 65 c to 150 c (note 1) 32 33 pgnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 sw1 tg1 pgood1 track/ss1 i th1 v fb1 sense1 + sense1 ? intv cc nc ov2 sgnd sgnd run2 sgnd run1 boost1 bg1 sw2 tg2 boost2 bg2 v bias extv cc freq ? pllin/mode ss2 sense2 + sense2 ? v fb2 i th2 sgnd t jmax = 150c, q ja = 44c/w exposed pad (pin 33) is pgnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc7812euh#pbf ltc7812euh#trpbf 7812 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc7812iuh#pbf ltc7812iuh#trpbf 7812 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc7812huh#pbf ltc7812huh#trpbf 7812 32-lead (5mm 5mm) plastic qfn C40c to 150c c onsult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www .linear.com/product/ltc7812#orderinfo ltc7812 7812fc
3 for more information www.linear.com/ltc7812 electrical characteristics symbol parameter conditions min typ max units v bias bias input supply operating voltage range 4.5 38 v v out1 buck regulated output voltage set point (sense1 pins common mode range) 0.8 24 v v out2 boost regulated output voltage set point 60 v sense2 pins common mode range (boost converter input supply voltage) 2.5 38 v v fb1 buck regulated feedback voltage (note 4); i th1 voltage = 1.2v 0c to 85c, all grades ltc7812e, ltc7812i ltc7812h l l 0.792 0.788 0.786 0.800 0.800 0.800 0.808 0.812 0.812 v v v v fb2 boost regulated feedback voltage (note 4); i th2 voltage = 1.2v 0c to 85c, all grades ltc7812e, ltc7812i ltc7812h l l 1.183 1.181 1.176 1.200 1.200 1.200 1.214 1.218 1.218 v v v i fb1, 2 feedback current (note 4) C2 50 na reference voltage line regulation (note 4); v in = 4.5v to 38v 0.002 0.02 %/v output voltage load regulation (note 4) measured in servo loop; di th voltage = 1.2v to 0.7v l 0.01 0.1 % measured in servo loop; di th voltage = 1.2v to 2v l C 0.01 C0.1 % g m1, 2 transconductance amplifier g m (note 4); i th1, 2 = 1.2v; sink/ source 5a 2 mmho i q input dc supply current (note 5) pulse-skipping or forced continuous mode (one channel on) run1 = 5v and run 2 = 0v or run2 = 5v and run1 = 0v v fb1 on = 0.83v (no load) v fb2 = 1.25v (no load) 1.5 ma pulse-skipping or forced continuous mode (both channels on) run1,2 = 5v, v fb1 = 0.83v (no load) v fb2 = 1.25v (no load) 3 ma sleep mode (one channel on, buck) run1 = 5v and run2 = 0v v fb1 = 0.83v (no load) l 28 48 a sleep mode (one channel on, boost) run2 = 5v and run1 = 0v v fb2 = 1.25v (no load) 33 53 a sleep mode (both channels on) run1,2 = 5v v fb1 = 0.83v (no load) v fb2 = 1.25v (no load) 33 46 a shutdown run1, 2 = 0v 10 20 a uvlo undervoltage lockout intv cc ramping up l 4.15 4.5 v intv cc ramping down l 3.5 3.8 4.0 v buck feedback overvoltage protection measured at v fb1 relative to regulated v fb1 7 10 13 % sense1 + pin current 1 a sense2 + pin current 170 a sense1 C pin current v out1 < v intvcc C 0.5v v out1 > v intvcc + 0.5v 700 2 a a sense2 C pin current v sense2 +, v sense2 C = 12v 1 a the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted. (note 2) ltc7812 7812fc
4 for more information www.linear.com/ltc7812 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted. (note 2) symbol parameter conditions min typ max units maximum duty factor for tg buck (channel 1) in dropout, freq = 0v boost (channel 2) in overvoltage 98 99 100 % % maximum duty factor for bg buck (channel 1) in overvoltage boost (channel 2) 100 96 % % i track/ss1 soft-start charge current v track/ss1 = 0v 3 5 8 a i ss2 soft-start charge current v ss2 = 0v 3 5 8 a v run1 on v run2 on run1 pin threshold run2 pin threshold v run1 rising v run2 rising l l 1.18 1.21 1.24 1.27 1.32 1.33 v v run pin hysteresis 70 mv v sense1,2,(max) maximum current sense threshold v fb1 = 0.7v, v sense1 C = 3.3v v fb2 = 1.1v, v sense2 + = 12v l 43 50 57 mv gate driver tg1 pull-up on-resistance tg1 pull-down on-resistance 2.5 1.5 ? ? bg1 pull-up on-resistance bg1 pull-down on-resistance 2.4 1.1 ? ? tg2 pull-up on-resistance tg2 pull-down on-resistance 1.2 1.0 ? ? bg2 pull-up on-resistance bg2 pull-down on-resistance 1.2 1.0 ? ? tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 16 ns ns bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 28 13 ns ns top gate off to bottom gate on delay synchronous switch -on delay time c load = 3300pf each driver buck (channel 1) boost (channel 2) 30 70 ns ns bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver buck (channel 1) boost (channel 2) 30 70 ns ns t on(min)1 buck minimum on- time (note 7) 95 ns t on(min)2 boost minimum on- time (note 7) 120 ns intv cc linear regulator internal v cc voltage 6v < v bias < 38v, v extvcc = 0v, i intvcc = 0ma 5.0 5.4 5.6 v intv cc load regulation i cc = 0ma to 50ma, v extvcc = 0v 0.7 2 % internal v cc voltage 6v < v extvcc < 13v, i intvcc = 0ma 5.0 5.4 5.6 v intv cc load regulation i cc = 0ma to 50ma, v extvcc = 8.5v 0.7 2 % extv cc switchover voltage extv cc ramping positive 4.5 4.7 v extv cc hysteresis 200 mv oscillator and phase-locked loop programmable frequency r freq = 25k; pllin/mode = dc voltage 115 khz r freq = 65k; pllin/mode = dc voltage 440 khz r freq = 105k; pllin/mode = dc voltage 835 khz low fixed frequency v freq = 0v pllin/mode = dc voltage 320 350 380 khz ltc7812 7812fc
5 for more information www.linear.com/ltc7812 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted. (note 2) symbol parameter conditions min typ max units high fixed frequency v freq = intv cc ; pllin/mode = dc voltage 485 535 585 khz synchronizable frequency pllin/mode = external clock l 75 850 khz pgood1 output pgood1 voltage low i pgood1 = 2ma 0.2 0.4 v pgood1 leakage current v pgood1 = 5v 1 a pgood1 trip level v fb1 with respect to set regulated voltage v fb1 ramping negative C13 C10 C7 % hysteresis 2.5 % v fb1 ramping positive 7 10 13 % hysteresis 2.5 % delay for reporting a fault 40 s ov2 boost overvoltage indicator output ov2 voltage low i ov2 = 2ma 0.2 0.4 v ov2 leakage current v ov2 = 5v 1 a ov2 trip level v fb2 ramping positive with respect to set regulated voltage 6 10 13 % hysteresis 1.5 % boost2 charge pump boost2 charge pump available output current v boost2 = 16v; v sw2 = 12v; forced continuous mode 65 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc7812 is tested under pulsed load conditions such that t j t a . the ltc7812e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc7812i is guaranteed over the C40c to 125c operating junction temperature range and the ltc7812h is guaranteed over the C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? q ja ), where q ja = 44c/w. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc7812 is tested in a feedback loop that servos v ith1,2 to a specified voltage and measures the resultant v fb . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the ltc7812e/ltc7812i, 150c for the ltc7812h). for the ltc7812i and ltc7812h, the specification at 0c is not tested in production and is assured by design, characterization and correlation to production testing at C40c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see the applications information section. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see the minimum on- time considerations in the applications information section). note 8: do not apply a voltage or current source to these pins. they must be connected to capacitive loads only, otherwise permanent damage may occur. ltc7812 7812fc
6 for more information www.linear.com/ltc7812 typical performance characteristics power loss vs load current v in = 9v power loss vs load current v in = 14v power loss vs load current v in = 18v efficiency vs input voltage efficiency vs load current v in = 9v efficiency vs load current v in = 14v efficiency vs load current v in = 18v temperature (c) ?75 regulated feedback voltage (mv) 808 806 802 798 794 804 800 796 792 0 25 50 75 150 125 100 ?50 7812 g08 ?25 temperature (c) ?75 regulated feedback voltage (v) 1.212 1.209 1.203 1.191 1.194 1.197 1.206 1.200 1.188 0 25 50 75 150 120 100 ?50 7812 g09 ?25 buck regulated feedback voltage vs temperature boost regulated feedback voltage vs temperature ltc7812 7812fc 15 9 0.001 0.01 0.1 1 10 power loss (w) 7812 g05 burst mode operation pulse-skipping mode 20 forced continuous mode v out = 12v figure 9 circuit load current (a) 0.0001 0.001 0.01 0.1 1 9 25 0.001 0.01 0.1 1 10 power loss (w) 7812 g06 burst mode operation pulse-skipping mode forced continuous mode 30 v out = 12v figure 9 circuit load current (a) 0.0001 0.001 0.01 0.1 1 9 0 35 10 20 30 40 50 60 70 80 90 100 40 efficiency (%) 7812 g03 burst mode operation pulse-skipping mode forced continuous mode v out = 12v figure 9 circuit 90 92 93 95 figure 9 circuit 97 98 100 efficiency (%) 7812 g07 v out = 12v figure 9 circuit load current (a) 0.0001 0.001 v out = 12v 0.01 0.1 1 9 0 10 20 30 40 50 i out = 4a 60 70 80 90 100 efficiency (%) 7812 g01 burst mode operation pulse-skipping mode forced continuous mode i out = 8a load current (a) 0.0001 0.001 0.01 0.1 1 9 0 10 20 input voltage (v) 30 40 50 60 70 80 90 100 efficiency (%) 7812 g02 0 burst mode operation pulse-skipping mode forced continuous mode v out = 12v figure 9 circuit load current (a) 0.0001 0.001 0.01 0.1 5 1 9 0.001 0.01 0.1 1 10 power loss (w) 7812 g04 burst mode operation 10 pulse-skipping mode forced continuous mode v out = 12v figure 9 circuit load current (a) 0.0001 0.001 0.01 0.1 1
7 for more information www.linear.com/ltc7812 typical performance characteristics load step at v in = 18v forced continuous mode load step at v in = 9v pulse-skipping mode load step at v in = 14v pulse-skipping mode load step at v in = 18v pulse-skipping mode load step at v in = 9v forced continuous mode load step at v in = 14v forced continuous mode load step at v in = 9v burst mode operation load step at v in = 14v burst mode operation load step at v in = 18v burst mode operation figure 9 circuit v out = 12v v out 1v/div ac- coupled i l1 2a/div 200s/div 7812 g10 figure 9 circuit v out = 12v v out 1v/div ac- coupled i l1 2a/div 200s/div 7812 g11 figure 9 circuit v out = 12v v out 1v/div ac- coupled i l1 2a/div 200s/div 7812 g12 figure 9 circuit v out = 12v v out 500mv/div ac- coupled i l1 2a/div 200s/div 7812 g13 figure 9 circuit v out = 12v v out 500mv/div ac- coupled i l1 2a/div 200s/div 7812 g14 figure 9 circuit v out = 12v v out 500mv/div ac- coupled i l1 2a/div 200s/div 7812 g15 figure 9 circuit v out = 12v v out 500mv/div ac- coupled i l1 2a/div 200s/div 7812 g16 figure 9 circuit v out = 12v v out 500mv/div ac- coupled i l1 2a/div 200s/div 7812 g17 figure 9 circuit v out = 12v v out 500mv/div ac- coupled i l1 2a/div 200s/div 7812 g18 ltc7812 7812fc
8 for more information www.linear.com/ltc7812 typical performance characteristics sense pins total input current vs v sense voltage buck sense1 C pin input bias current vs temperature boost sense pin total input current vs temperature intv cc line regulation buck inductor current at light load intv cc and extv cc vs load current boost inductor current at light load extv cc switchover and intv cc voltages vs temperature start-up input voltage (v) 0 intv cc voltage (v) 5.5 5.4 5.2 5.3 5.1 5.0 15 20 25 30 35 40 5 7812 g22 10 load current (ma) 0 intv cc voltage (v) 5.6 5.2 5.4 4.6 4.8 5.0 4.4 4.2 4.0 60 80 100 20 7812 g23 40 extv cc = 0v extv cc = 5v extv cc = 8.5v v bias = 12v temperature (c) ?75 extv cc and intv cc voltage (v) 6.0 5.8 5.4 5.2 4.4 4.2 4.6 4.8 5.6 5.0 4.0 0 25 50 75 150 125 100 ?50 7812 g24 ?25 intv cc extv cc rising extv cc falling v sense common mode voltage (v) 0 sense current (a) 800 700 400 500 300 100 200 600 0 15 20 25 30 35 40 5 7812 g25 10 sense1 pin sense2 pin temperature (c) ?75 sense current (a) 200 160 180 100 120 80 40 20 60 140 0 0 25 50 75 100 125 150 ?50 7812 g27 ?25 sense2 + pin sense2 ? pin v in = 12v temperature (c) ?75 sense1 ? current (a) 900 700 800 400 500 300 100 200 600 0 0 25 50 75 100 125 150 ?50 7812 g26 ?25 v out < intv cc ? 0.5v v out > intv cc + 0.5v figure 9 circuit v in = 18v v out = 12v i out = 1ma i l1 2a/div 5s/div 7812 g19 forced continuous mode pulse-skipping mode burst mode operation figure 9 circuit v in = 8v v out = 12v i out = 1ma i l2 5a/div 5s/div 7812 g20 forced continuous mode pulse-skipping mode burst mode operation figure 9 circuit v in = 8v v out = 12v i out = 0ma 2v/div 2v/div 5s/div 7812 g21 v out run pins ltc7812 7812fc
9 for more information www.linear.com/ltc7812 maximum current sense threshold vs duty cycle maximum current sense threshold vs i th voltage track/ss1 and ss2 pull-up current vs temperature duty cycle (%) 0 maximum current sense voltage (mv) 80 60 70 30 40 20 10 50 0 50 60 70 80 90 100 10 7812 g28 20 30 40 boost buck i th (v) 0 maximum current sense voltage (mv) 60 40 50 ?10 0 ?20 30 20 10 ?30 1 1.2 1.4 0.2 7812 g29 0.4 0.6 0.8 burst mode operation pulse-skipping forced continuous duty cycle = 10% temperature (c) ?75 track/ss current (a) 6.00 5.75 5.25 5.00 4.25 4.50 5.50 4.75 4.00 0 25 50 75 125 100 150 ?50 7812 g30 ?25 typical performance characteristics buck foldback current limit oscillator frequency vs temperature shutdown current vs temperature shutdown current vs input voltage quiescent current vs temperature temperature (c) ?75 shutdown current (a) 20 16 14 10 18 12 4 6 8 0 25 50 75 100 125 150 ?50 7812 g31 ?25 v bias = 12v v bias input voltage (v) 5 shutdown current (a) 25 20 15 5 10 0 20 25 30 35 40 10 7812 g32 15 temperature (c) ?75 quiescent current (a) 80 50 60 70 0 10 20 30 40 0 25 50 75 100 125 150 ?50 7812 g33 ?25 channel 1 on both channels on v fb1 feedback voltage (mv) 0 maximum current sense voltage (mv) 70 60 50 20 10 30 40 65 55 45 15 5 25 35 0 300 400 500 600 700 800 100 7812 g34 200 temperature (c) ?75 frequency (khz) 600 550 500 350 400 450 300 0 25 50 75 100 125 150 ?50 7812 g35 ?25 freq = intv cc freq = gnd ltc7812 7812fc
10 for more information www.linear.com/ltc7812 shutdown (run) threshold vs temperature charge pump charging current vs operating frequency charge pump charging current vs switch voltage temperature (c) ?75 run pin voltage (v) 1.40 1.35 1.30 1.20 1.00 1.15 1.10 1.05 1.25 0 25 50 75 100 125 150 ?50 7812 g37 ?25 run1 rising run1 falling run2 falling run2 rising operating frequency (khz) 100 charge pump charging current (a) 100 80 90 60 70 20 30 0 10 40 50 400 500 600 700 800 200 7812 g38 300 ?55c 25c 150c v boost2 = 16v v sw2 = 12v switch voltage (v) 5 charge pump charging current (a) 100 80 90 60 70 20 30 0 10 40 50 20 25 30 35 40 10 7812 g39 freq = 0v freq = intv cc 15 v boost2 ? v sw2 = 4v typical performance characteristics undervoltage lockout threshold vs temperature temperature (c) ?75 intv cc voltage (v) 4.4 4.3 4.2 3.6 3.8 4.0 3.4 3.5 3.7 3.9 4.1 0 25 50 75 100 125 150 ?50 7812 g36 ?25 rising falling ltc7812 7812fc
11 for more information www.linear.com/ltc7812 pin functions sw1, sw2 (pins 1, 30): switch node connections to inductors. tg1, tg2, (pins 2, 29): high current gate drives for top n-channel mosfets . these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltage sw. pgood1 (pin 3): open-drain logic output. pgood1 is pulled to ground when the voltage on the v fb1 pin is not within 10% of its set point. track/ss1, ss2 (pins 4,11): external tracking and soft- start input. for the buck channel, the ltc7812 regulates the v fb1 voltage to the smaller of 0.8v or the voltage on the track/ss1 pin. for the boost channel, the ltc7812 regulates the v fb2 voltage to the smaller of 1.2v or the voltage on the ss2 pin. an internal 5a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to final regulated output voltage. alternatively, a resistor divider on another voltage supply connected to the track/ss1 pin allow the ltc7812 buck output to track another supply during start-up. i th1 , i th2 ( pins 5, 15): error amplifier outputs and switch - ing regulator compensation points. each associated channels current comparator trip point increases with this control voltage. v fb1 , v fb2 (pins 6, 14): receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. sense1 + , sense2 + (pins 7, 12): the (+) input to the differential current comparators. the i th pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. for the boost channel, the sense2 + pin supplies current to the current comparator. sense1 C , sense2 C (pins 8, 13): the (C) input to the dif - ferential current comparators. when sense1 C is greater than intv cc , then sense1 C pin supplies current to the current comparator for the buck channel. freq (pin 9): the frequency control pin for the internal vco. connecting the pin to gnd forces the vco to a fixed low frequency of 350khz. connecting the pin to intv cc forces the vco to a fixed high frequency of 535khz. other frequencies between 50khz and 900khz can be programmed using a resistor between freq and gnd. the resistor and an internal 20a source current create a voltage used by the internal oscillator to set the frequency. pllin/mode (pin 10): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, the phase-locked loop will force the rising tg1 and bg2 signals to be syn - chronized with the rising edge of the external clock, and the regulators operate in forced continuous mode. when not synchronizing to an external clock, this input, which acts on both controllers, determines how the ltc7812 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2v and less than intv cc C 1.3v selects pulse-skipping operation. this can be done by connecting a 100k resistor from this pin to intv cc . sgnd (pins 16, 18, 20, 21): small signal ground com - mon to both controllers. all four pins must be tied together near the ltc7812 and must be routed separately from high current grounds to the common (C) terminals of the c in capacitors. run1, run2 (pins 17, 19): run control inputs for each controller. forcing run1 below 1.17v and run2 below 1.20v shuts down that controller . forcing both of these pins below 0.7v shuts down the entire ltc7812, reducing quiescent current to approximately 10a. ltc7812 7812fc
12 for more information www.linear.com/ltc7812 pin functions v bias (pin 26): main bias input supply pin. a bypass ca - pacitor should be tied between this pin and the sgnd pins. bg1, bg2 (pins 31, 27): high current gate drives for bottom n-channel mosfets . voltage swing at these pins is from ground to intv cc . boost1, boost2 (pins 32, 28): bootstrapped supplies to the top side floating drivers. capacitors are connected between the boost and sw pins and schottky diodes are tied between the boost and intv cc pins. voltage swing at the boost1 pin is from intv cc to (v in + intv cc ) and at the boost2 pin is from intv cc to (v out + intv cc ). pgnd (exposed pad pin 33): driver power ground. con - nects to the sources of bottom n - channel mosfets and the (C) terminal(s) of c in . the exposed pad must be soldered to the pcb for rated electrical and thermal performance. ov2 (pin 22): overvoltage open-drain logic output for the boost regulator. ov2 is pulled to ground when the voltage on the v fb2 pin is under 110% of its set point, and becomes high impedance when v fb2 goes over 110% of its set point. nc (pin 23): no connect. no external connection is re - quired. this pin may be left floating or tied to another node. intv cc ( pin 24): output of the internal linear low dropout regulator. the driver and control circuits are powered from this voltage source . must be decoupled to pgnd with a minimum of 4.7f ceramic or tantalum capacitor. extv cc (pin 25): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power, bypassing the internal ldo powered from v bias whenever extv cc is higher than 4.7v. see extv cc connection in the applications information section. do not float or exceed 14v on this pin. ltc7812 7812fc
13 for more information www.linear.com/ltc7812 functional diagram 3859al fda switching logic intv cc v in1 d b c b boost1 tg1 sw1 bg1 pgnd sense1 + sense1 ? c in d c out intv cc l r sense top bot dropout det s q r q bot topon shdn + ? sleep + ? + ? + ? + ? icmp ir 2.8v 0.65v slope comp v fb1 i th1 3mv 0.80v track/ss 0.88v + ? ? + + track/ss1 ov c c2 r c c c run1 c ss foldback shdn r st 2(v fb ) shdn 7a 11v pfd vco c lp clk sync det 20a 100k r a r b ldo en ldo en + ? 4.7v 5.4v 5.4v intv cc sgnd extv cc v bias pllin/mode freq pgood1 + ? + ? 0.88v 0.72v v fb1 ea buck channel 1 5a v out1 6.8v ltc7812 7812fc
14 for more information www.linear.com/ltc7812 functional diagram 3859al fdb switching logic intv cc v out2 d b c b boost2 tg2 sw2 bg2 pgnd sense2 + sense2 ? c out c in intv cc l r sense top bot s q r q boton shdn + ? sleep + ? + ? + ? + ? icmp ir 2.8v 0.7v slope comp v fb2 i th2 2mv 1.2v ss2 1.32v + ? ? + + ss2 ov c c2 r c c c run2 c ss shdn snslo 160na 11v r a r b ea + ? 2v snslo clk pllin/mode + ? v fb2 1.32v ov2 0.425v boost channel 2 5a v in2 v out2 ltc7812 7812fc
15 for more information www.linear.com/ltc7812 operation main control loop the ltc7812 uses a constant frequency, current mode control architecture . channel 1 is a buck (step-down) controller and channel 2 is a boost (step-up) control - ler. during normal operation, the external top mosfet for the buck channel (the external bottom mosfet for the boost channel) is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the i th pin, which is the output of the error amplifier ea. the error amplifier compares the output voltage feedback signal at the v fb pin, (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage for the buck (1.2v reference voltage for the boost). when the load current increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the i th voltage until the average inductor current matches the new load current. after the top mosfet for the buck (the bottom mosfet for the boost) is turned off each cycle, the bottom mosfet is turned on (the top mosfet for the boost) until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc / extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, the v bias ldo (low dropout linear regulator) supplies 5.4v from v bias to intv cc . if extv cc is taken above 4.7v, the v bias ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies 5.4v from extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as one of the ltc7812 switching regulator outputs. each top mosfet driver is biased from the floating boot - strap capacitor c b , which normally recharges during each cycle through an external diode when the switch voltage goes low. for buck channel 1 if the bucks input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one twelfth of the clock period every tenth cycle to allow c b to recharge. this gives tg1 an effective duty cycle of 99% in dropout. shutdown and start- up ( run1, run2, and track / ss 1, ss2 pins) the two channels of the ltc7812 can be independently shut down using the run1 and run2 pins. pulling run1 below 1.17v or run2 below 1.20v shuts down the main control loop for that channel. pulling both pins below 0.7v disables both controllers and most internal circuits , including the intv cc ldos. in this state, the ltc7812 draws only 10a of quiescent current. releasing a run pin allows a small internal current to pull up the pin to enable that controller . the run 1 pin has a 7a pull-up current while the run2 pin has a smaller 160na. the 7a current on run1 is designed to be large enough so that the run1 pin can be safely floated (to always en - able the controller) without worry of condensation or other small board leakage pulling the pin down. this is ideal for always-on applications where one or both controllers are enabled continuously and never shut down. if it is desired that both channels remain on always, run2 can be tied to run1 with the connection floated. each run pin may also be externally pulled up or driven directly by logic. when driving a run pin with a low imped - ance source , do not exceed the absolute maximum rating of 8v. each run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v bias ), so long as the maximum current in the run pin does not exceed 100a. the start-up of each channels output voltage v out is con - trolled by the voltage on the track/ss pin (track/ss1 for channel 1, ss2 for channel 2). when the voltage on (refer to functional diagram) ltc7812 7812fc
16 for more information www.linear.com/ltc7812 operation the track/ss pin is less than the 0.8v internal reference for the buck and the 1.2v internal reference for the boost, the ltc7812 regulates the v fb voltage to the track/ss pin voltage instead of the corresponding reference voltage. this allows the track/ ss pin to be used to program a soft- start by connecting an external capacitor from the track/ ss pin to sgnd. an internal 5a pull-up current charges this capacitor creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from 0v to 0.8v/1.2v (and beyond up to intv cc ), the output voltage v out rises smoothly from zero to its final value. alternatively the track/ ss pin for buck channel 1 can be used to cause the start- up of v out to track that of another supply. typically , this requires connecting to the track/ ss pin an external resistor divider from the other supply to ground ( see the applications information section). light load current operation (burst mode operation, pulse-skipping, or forced continuous conduction) (pllin/mode pin) the ltc7812 can be enabled to enter high efficiency burst mode operation, constant frequency pulse-skipping mode or forced continuous conduction mode at low load cur - rents. to select burst mode operation, tie the pllin/ mode pin to ground. to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when a controller is enabled for burst mode operation, the minimum peak current in the inductor is set to approxi - mately 25% of the maximum sense voltage (30% for the boost) even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the i th pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc7812 draws. if the buck channel 1 is in sleep mode and the boost channel 2 is shut down, the ltc7812 draws only 28a of quies - cent current. if both channels are in sleep mode, it draws only 33a of quiescent current. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise. when the output voltage drops enough, the i th pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (ir) turns off the bottom external mosfet (the top external mosfet for the boost) just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation or when clocked by an external clock source to use the phase-locked loop (see the frequency selection and phase-locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur - rent is determined by the voltage on the i th pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry . in forced continuous mode, the output ripple is independent of load current. when the pllin/ mode pin is connected for pulse- skipping mode, the ltc7812 operates in pwm pulse-skipping mode at light loads. in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator icmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. ltc7812 7812fc
17 for more information www.linear.com/ltc7812 operation frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc7812s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source , the freq pin can be tied to sgnd, tied to intv cc , or programmed through an external resistor. tying freq to sgnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and sgnd allows the frequency to be programmed between 50khz and 900khz as shown in figure 7. a phase-locked loop (pll) is available on the ltc7812 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the ltc7812s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of tg1 and bg2 to the rising edge of the syn - chronizing signal. the vco input voltage is pre-biased to the operating frequency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of tg1. the ability to pre-bias the loop filter allows the pll to lock in rapidly without deviating far from the desired frequency. the typical capture range of the ltc7812s phase-locked loop is from approximately 55khz to 1mhz, with a guar - antee over all manufacturing variations to be between 75khz and 850khz. in other words, the ltc7812s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). boost controller operation when v in > v out when the input voltage to the boost channel rises above its regulated v out voltage, the controller can behave dif - ferently depending on the mode, inductor current and v in voltage. in forced continuous mode, the loop works to keep the top mosfet on continuously once v in rises above v out . an internal charge pump delivers current to the boost capacitor from the boost2 pin to maintain a sufficiently high tg voltage. (the amount of current the charge pump can deliver is characterized by two curves in the typical performance characteristics section.) in pulse-skipping mode, if v in is between 100% and 110% of the regulated v out voltage, tg2 turns on if the inductor current rises above approximately 3% of the programmed i lim current. if the part is programmed in burst mode operation under this same v in window, then tg2 turns on at the same threshold current as long as the chip is awake (the buck channel is awake and switching). if the buck channel is asleep or shut down in this v in window, then tg2 will remain off regardless of the inductor current. if v in rises above 110% of the regulated v out voltage in any mode, the controller turns on tg2 regardless of the inductor current. in burst mode operation, however, the internal charge pump turns off if the entire chip is asleep (the buck channel is asleep or shut down). with the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient tg2 voltage needed to keep the top mosfet completely on. the charge pump turns back on when the chip wakes up, and it remains on as long as one of the buck channels is actively switching. boost controller at low sense pin common voltage the current comparator of the boost controller is powered directly from the sense2 + pin and can operate to voltages as low as 2.5v . since this is lower than the v bias uvlo of the chip, v bias can be connected to the output of the boost controller , as illustrated in the typical application circuit in figure 12. this allows the boost controller to handle input voltage transients down to 2.5v while maintaining output voltage regulation. if the sense2 + rises back above 2.5v, the ss2 pin will be released initiating a new soft-start sequence. ltc7812 7812fc
18 for more information www.linear.com/ltc7812 buck controller output overvoltage protection the buck channel has an overvoltage comparator that guards against transient overshoots as well as other more serious conditions that may overvoltage its output. when the v fb1 pin rises by more than 10% above its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condi - tion is cleared. buck power good (pgood1) channel 1 has a pgood1 pin that is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood1 pin low when the v fb1 pin voltage is not within 10% of the 0.8v reference voltage for the buck channel. the pgood1 pin is also pulled low when the run1 pin is low (shut down). when the v fb1 pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. boost overvoltage indicator (ov2) the ov2 pin is an overvoltage indicator that signals whether the output voltage of the channel 2 boost controller goes over its programmed regulated voltage. the pin is con - nected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the ov2 pin low when the v fb2 pin voltage is less than 110% of the 1.2v reference voltage for the boost channel. the ov2 pin is also pulled low when the run2 pin is low (shut down). when the v fb2 pin voltage goes higher than 110% of the 1.2v reference, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. buck foldback current when the buck output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short- circuit condition. foldback current limiting is disabled during the soft-start interval (as long as the v fb1 voltage is keeping up with the track/ss1 voltage). there is no foldback current limiting for the boost channel. operation ltc7812 7812fc
19 for more information www.linear.com/ltc7812 figure 1. sense lines placement with inductor or sense resistor applications information cascaded boost+buck regulator the ltc7812 can be configured to regulate two separate, completely independent outputs, one boost and one buck. or, it can be configured as a cascaded boost+buck single output converter that regulates an output voltage from an input voltage that can be above, below, or equal to the output voltage. when cascaded, the input voltage feeds the boost regulator, which generates an intermediate node supply (v mid ) that then serves as the input to the buck regulator, which then regulates the output voltage. when used as a cascaded boost+buck regulator, the ltc7812 has distinct advantages compared to traditional single inductor buck-boost regulators. even though it requires two inductors, these inductors are individually smaller and provide inherent filtering at the input and output, substantially reducing conducted emi and volt - age ripple, thereby requiring less input and output filter - ing. even though they are cascaded, the boost and buck regulators are independently optimized and compensated. the buck regulator on the output provides a very fast transient response compared to a buck-boost regulator, further reducing the amount of output capacitance that is required. the ltc7812 also features a very low quiescent current burst mode operation which dramatically reduces power loss and increases efficiency at light loads. thus, for those applications that require low emi, low ripple, fast transient response, low quiescent current, and/ or high light load efficiency, the ltc7812 cascaded boost+buck regulator provides an excellent solution. the typical application on the first page is a basic ltc7812 application circuit . ltc7812 can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. buck controller (sense1 + /sense 1 C ): the common mode voltage range on these pins is 0v to 28v (absolute maxi - mum), enabling the ltc7812 to regulate a buck output voltage up to a nominal 24v set point (allowing margin for tolerances and transients). the sense1 + pin is high impedance over the full common mode range, drawing at most 1a. this high impedance allows the current comparators to be used in inductor dcr sensing. the impedance of the sense1 C pin changes depending on the common mode voltage. when sense1 C is less than intv cc C 0.5v, a small current of less than 1a flows out of the pin. when sense1 C is above intv cc + 0.5v, a higher current ( 700a ) flows into the pin. between intv cc C 0.5v and intv cc + 0.5v , the current transitions from the smaller current to the higher current. boost controller ( sense2 + / sense2 C ): the common mode input range for these pins is 2.5v to 38v , allowing the boost converter to operate from inputs over this full range. the sense2 + pin also provides power to the current compara - tor and draws about 170a during normal operation ( when not shut down or asleep in burst mode operation). there is a small bias current of less than 1a that flows out of the sense2 C pin. this high impedance on the sense2 C pin allows the current comparator to be used in inductor dcr sensing. filter components mutual to the sense lines should be placed close to the ltc7812, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cur - 7812 f01 to sense filter next to the controller inductor or r sense current flow ltc7812 7812fc
20 for more information www.linear.com/ltc7812 applications information rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparators have a maximum threshold v sense(max) of 50mv. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, di l . to calculate the sense resistor value, use the equation: r s e n s e = v s e n s e ( m a x ) i m a x + d i l 2 when using the controller in very high duty cycle condi - tions, the maximum output current level will be reduced due to the internal compensation required to meet stabil - ity criterion for switching regulators operating at greater than 50% duty factor. a curve is provided in the typical performance characteristics section to estimate this re - duction in peak output current level depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc7812 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing . if the external r1||r 2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r 2/(r 1 + r 2). r 2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. 2b. using the inductor dcr to sense current 2a. using a resistor to sense current figure 2. current sensing methods 7812 f02a ltc7812 intv cc boost tg sw bg sense1 + (sense2 ? ) sense1 ? (sense2 + ) sgnd v in1 (v out2 ) v out1 (v in2 ) r sense cap placed near sense pins 7812 f02b ltc7812 intv cc boost tg sw bg sense1 + (sense2 ? ) sense1 ? (sense2 + ) sgnd v in1 (v out2 ) v out1 (v in2 ) c1* r2 *place c1 near sense pins r sense(eq) = dcr(r2/(r1+r2)) l dcr inductor r1 (r1||r2) ? c1 = l/dcr ltc7812 7812fc
21 for more information www.linear.com/ltc7812 applications information using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r ( e q u i v ) = v s e n s e ( m a x ) i m a x + d i l 2 to ensure that the application will deliver full load cur - rent over the full operating temperature range, determine r sense(equiv) , keeping in mind that the maximum current sense threshold (v sense(max) ) for the ltc7812 is fixed at 50mv. next, determine the dcr of the inductor. where provided, use the manufacturer s maximum value, usually given at 20c. increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r s e n s e ( e q u i v ) d c r m a x a t t l ( m a x ) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1||r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current. the equivalent resistance r1||r2 is scaled to the room temperature inductance and maximum dcr: ? r 1 ? r 2 = l ( d c r a t 20 c ) ? c 1 the sense resistor values are: ? r 1 = r 1 ? r 2 r d ; r 2 = r 1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle. for the buck controllers, the maximum power loss will occur in continuous mode at the maximum input voltage: p l o s s r 1 = ( v i n ( m a x ) ? v o u t ) ? v o u t r 1 for the boost controller, the maximum power loss in r1 will occur in continuous mode at v in = 1/2 ? v out : p l o s s r 1 = ( v o u t ( m a x ) ? v i n ) ? v i n r 1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current di l decreases with higher inductance or frequency. for the buck controller, di l increases with higher v in : d i l = 1 ( f ) ( l ) v o u t 1 ? v o u t v i n ? ? ? ? ? ? for the boost controller, the inductor ripple current di l increases with higher v out : d i l = 1 ( f ) ( l ) v i n 1 ? v i n v o u t ? ? ? ? ? ? accepting larger values of di l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is di l = 0.3(i max ). the maximum di l occurs at the maximum input voltage for the buck and v in = 1/2 ? v out for the boost. ltc7812 7812fc
22 for more information www.linear.com/ltc7812 applications information the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit (30% for the boost) determined by r sense . lower inductor values (higher di l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet selection tw o external power mosfets must be selected for each controller in the ltc7812: one n-channel mosfet for the top switch (main switch for the buck, synchronous for the boost), and one n-channel mosfet for the bottom switch (main switch for the boost, synchronous for the buck). the peak- to- peak drive levels are set by the intv cc voltage. this voltage is typically 5.4v during start-up (see extv cc pin connection). consequently, logic- level threshold mosfets must be used in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: b uc k m a i n s wi t c h d ut y c y c l e = v o u t v i n b uc k s y nc s wi t c h d ut y c y c l e = v i n ? v o u t v i n b oos t m a i n s wi t c h d ut y c y c l e = v o u t ? v i n v o u t b oos t s y nc s wi t c h d ut y c y c l e = v i n v o u t the mosfet power dissipations at maximum output current are given by: p m a i n _ b u c k = v o u t v i n i o u t ( m a x ) ( ) 2 1+ ( ) r d s ( o n ) + ( v i n ) 2 i o u t ( m a x ) 2 ? ? ? ? ? ? ( r d r ) ( c m i l l e r ) ? 1 v i n t v c c ? v t h m i n + 1 v t h m i n ? ? ? ? ? ? ( f ) p s y n c _ b u c k = v i n ? v o u t v i n i o u t ( m a x ) ( ) 2 1+ ( ) r d s ( o n ) p m a i n _ b o o s t = v o u t ? v i n ( ) v o u t v i n 2 i o u t ( m a x ) ( ) 2 ? 1 + ( ) r d s ( o n ) + v o u t 3 v i n ? ? ? ? ? ? i o u t ( m a x ) 2 ? ? ? ? ? ? ? r d r ( ) c m i l l e r ( ) ? 1 v i n t v c c ? v t h m i n + 1 v t h m i n ? ? ? ? ? ? ( f ) p s y n c _ b o o s t = v i n v o u t i o u t ( m a x ) ( ) 2 1 + ( ) r d s ( o n ) ltc7812 7812fc
23 for more information www.linear.com/ltc7812 applications information where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfet s miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the main n-channel equations for the buck and boost controllers include an additional term for transition losses, which are highest at high input voltages for the buck and low input voltages for the boost. for v in < 20v (high v in for the boost) the high current efficiency generally improves with larger mosfets , while for v in > 20v (low v in for the boost) the transition losses rapidly increase to the point that the use of a higher r ds( on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses for the buck controller are greatest at high input voltage when the top switch duty factor is low or during a short- circuit when the synchronous switch is on close to 100% of the period. the synchronous mosfet losses for the boost control - ler are greatest when the input voltage approaches the output voltage or during an overvoltage event when the synchronous switch is on 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve , but = 0.005/c can be used as an approximation for low voltage mosfets. boost c in , c out selection the input ripple current in a boost converter is relatively low (compared with the output ripple current), because this current is continuous. the boost input capacitor c in voltage rating should comfortably exceed the maximum input voltage. although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not . be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. the value of c in is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. in a boost converter, the output has a discontinuous current, so c out must be capable of reducing the output voltage ripple. the effects of esr ( equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady ripple due to charging and discharging the bulk capacitance is given by: r i ppl e = i o u t ( m a x ) ? v o u t ? v i n ( m i n ) ( ) c o u t ? v o u t ? f v where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: dv esr = i l(max) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings such as os-con and poscap. buck c in and c out selection the selection of c in is usually based off the worst- case rms input current. the highest (v out )(i out ) product needs to be used in the formula shown in equation 1 to determine the maximum rms capacitor current requirement. in continuous mode , the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c i n r e qui r e d i r m s i m a x v i n v o u t ( ) v i n ? v o u t ( ) ? ? ? ? 1 / 2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. ltc7812 7812fc
24 for more information www.linear.com/ltc7812 applications information this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc7812, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the ltc7812, is also suggested. a small (10) resistor placed between c in (c1) and the v in pin provides further isolation. the selection of c out is driven by the effective series resistance (esr). typically , once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (v out ) is approximated by: d v o u t d i l es r + 1 8 ? f ? c o u t ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. setting output voltage the ltc7812 output voltages are each set by an external feedback resistor divider carefully placed across the out - put, as shown in figure 3. the regulated output voltages are determined by: v o u t , b u c k = 0.8 v 1 + r b r a ? ? ? ? ? ? v o u t , b o o s t = 1.2 v 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feedforward ca - pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources , such as the inductor or the sw line. tracking and soft-start (track/ss1, ss2 pins) the start-up of each v out is controlled by the voltage on the respective track/ss pin (track/ss1 for channel 1, ss2 for channel 2). when the voltage on the track/ss pin is less than the internal 0.8v reference (1.2v reference for the boost channel), the ltc7812 regulates the v fb pin voltage to the voltage on the track/ss pin instead of the internal reference. likewise, the track/ss1 pin for the buck channel can be used to program an external soft- start function or to allow v out to track another supply during start-up. figure 3. setting output voltage 7812 f03 1/2 ltc7812 v fb r b c ff r a v out figure 4. using the track/ss pin to program soft-start soft-start is enabled by simply connecting a capacitor from the track/ss pin to ground, as shown in figure 4. an internal 5a current source charges the capacitor, providing a linear ramping voltage at the track/ss pin. the ltc7812 will regulate the v fb pin (and hence v out ) according to the voltage on the track/ss pin, allowing v out to rise smoothly from 0v to its final regulated value. the total soft-start time will be approximately: t s s _ b u c k = c s s ? 0.8 v 5a t s s _ b o o s t = c s s ? 1.2 v 5a 7812 f04 ltc7812 track/ss sgnd c ss ltc7812 7812fc
25 for more information www.linear.com/ltc7812 applications information 5a. coincident tracking 5b. ratiometric tracking figure 5. tw o different modes of output voltage tracking figure 6. using the track/ss pin for tracking 7812 f05a v x(master) v out(slave) output (v out ) time 7812 f05b v x(master) v out(slave) output (v out ) time 7812 f06 ltc7812 v fb1 track/ss1 r b r a v out r trackb r tracka v x alternatively, the track/ ss1 pin for the buck controller can be used to track another supply during start-up, as shown qualitatively in figures 5a and 5b. to do this, a resistor divider should be connected from the master supply (v x ) to the track/ss pin of the slave supply (v out ), as shown in figure 6. during start-up v out will track v x according to the ratio set by the resistor divider: v x v o u t = r a r t r a c k a ? r t r a c k a + r t r a c k b r a + r b for coincident tracking (v out = v x during start-up), r a = r tracka r b = r trackb intv cc regulators the ltc7812 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the intv cc pin from either the v bias supply pin or the extv cc pin depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the ltc7812s internal circuitry . the v bias ldo and the ex - tv cc ldo regulate intv cc to 5.4v. each of these must be bypassed to ground with a minimum of 4.7f ceramic capacitor . no matter what type of bulk capacitor is used , an additional 1f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc7812 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the v bias ldo or the extv cc ldo. when the voltage on the extv cc pin is less than 4.7v, the v bias ldo is enabled. power dissipation for the ic in this case is highest and is equal to v bias ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency consid - erations section. the junction temperature can be estimated ltc7812 7812fc
26 for more information www.linear.com/ltc7812 applications information by using the equations given in note 2 of the electrical characteristics. for example, the ltc7812 intv cc current is limited to less than 33ma from a 38v supply when not using the extv cc supply at a 70c ambient temperature in the qfn package: t j = 70c + (33ma)(38v)(44c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.7v , the v bias ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.5v . the extv cc ldo attempts to regulate the intv cc voltage to 5.4v , so while extv cc is less than 5.4v, the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 5.4v, up to an absolute maximum of 14v, intv cc is regulated to 5.4v. using the extv cc ldo allows the mosfet driver and control power to be derived from one of the ltc7812s switching regulator outputs (4.7 v v out 14v) dur - ing normal operation and from the v bias ldo when the output is out of regulation (e.g., startup, short- circuit). if more current is required through the extv cc ldo than is specified, an external schottky diode can be added between the extv cc and intv cc pins. in this case, do not apply more than 6v to the extv cc pin and make sure that extv cc v bias . significant efficiency and thermal gains can be realized by powering intv cc from the buck output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). for 5v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to a 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (33ma)(8.5v)(44c/w) = 82c however, for 3.3v and other low voltage outputs, additional circuitry is required to derive intv cc power from the output . the following list summarizes the four possible connec - tions for extv cc : 1. extv cc grounded. this will cause intv cc to be powered from the internal 5.4v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to the output voltage of one of the buck regulators. this is the normal connection for a 5v to 14v regulator and provides the highest ef - ficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc v bias . 4. extv cc connected to an output-derived boost network off one of the buck regulators. for 3.3v and other low voltage buck regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v . ensure that extv cc v bias . topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mos - fets . capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate- source of the desired mosfet . this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in for the buck channel (v out for the boost channel) and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc (v boost = v out + v intvcc for the boost controller). the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) for the buck channels and v out(max) for the boost channel. ltc7812 7812fc
27 for more information www.linear.com/ltc7812 applications information the external diode d b can be a schottky diode or silicon diode, but in either case it should have low leakage and fast recovery . pay close attention to the reverse leakage at high temperatures where it generally increases substantially. the topside mosfet driver for the boost channel includes an internal charge pump that delivers current to the bootstrap capacitor from the boost2 pin. this charge current maintains the bias voltage required to keep the top mosfet on continuously during dropout/ overvolt - age conditions. the schottky/silicon diode selected for the boost topside driver should have a reverse leakage less than the available output current the charge pump can supply. curves displaying the available charge pump current under different operating conditions can be found in the typical performance characteristics section. a leaky diode d b in the boost converter can not only prevent the top mosfet from fully turning on but it can also completely discharge the bootstrap capacitor c b and create a current path from the input voltage to the boost2 pin to intv cc . this can cause intv cc to rise if the diode leakage exceeds the current consumption on intv cc . this is particularly a concern in burst mode operation where the load on intv cc can be very small. there is an internal voltage clamp on intv cc that prevents the intv cc voltage from running away, but this clamp should be regarded as a failsafe only. the external schottky or silicon diode should be carefully chosen such that intv cc never gets charged up much higher than its normal regulation voltage. care should also be taken when choosing the external diode d b for the buck controller. a leaky diode not only increases the quiescent current of the buck converter, but it can also cause a similar leakage path to intv cc from v out for applications with output voltages greater than the intv cc voltage (~5.4v). fault conditions: buck current limit and current foldback the ltc7812 includes current foldback for the buck channels to help limit load current when the output is shorted to ground. if the buck output falls below 70% of its nominal output level, then the maximum sense volt - age is progressively lowered from 100% to 40% of its maximum selected value. under short- circuit conditions with very low duty cycles, the buck channel will begin cycle skipping in order to limit the short- circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on- time t on( min) of the ltc7812 (95ns), the input voltage and inductor value: di l(sc) = t on(min) (v in /l) the resulting average short- circuit current is: i s c = 40% ? i l i m ( m a x ) ? 1 2 d i l ( s c ) fault conditions: buck overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the buck regula - tor rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the buck output for overvoltage conditions. the comparator detects faults greater than 10% above the nominal output voltage. when this condi - tion is sensed, the top mosfet of the buck controller is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet for the buck channel will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. fault conditions: over temperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on chip (such as intv cc short to ground), the over temperature shutdown circuitry will shut down the ltc7812. when the junction temperature exceeds approximately 170c, the over temperature circuitry disables the intv cc ldo, caus - ing the intv cc supply to collapse and effectively shutting ltc7812 7812fc
28 for more information www.linear.com/ltc7812 applications information down the entire ltc7812 chip. once the junction tempera - ture drops back to approximately 155c, the intv cc ldo turns back on. long term overstress (t j > 125c) should be avoided as it can degrade the performance or shorten the life of the part. phase-locked loop and frequency synchronization the ltc7812 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (vco). this allows the turn-on of the tg1 and bg1 to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the phase detector is an edge sensitive digital type that provides nearly zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscil - lators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, holds the voltage at the vco input. note that the ltc7812 can only be synchronized to an external clock whose frequency is within range of the ltc7812s internal vco, which is nominally 55khz to 1 mhz. this is guaranteed to be between 75khz and 850khz. typically , the external clock (on pllin/mode pin) input high threshold is 1.6v , while the input low threshold is 1.2v . rapid phase-locking can be achieved by using the freq pin to set a free-running frequency near the desired synchronization frequency. the vcos input voltage is prebiased at a frequency correspond to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase-lock and synchronization. although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from pass - ing through a large range of frequencies as the pll locks. table 1 summarizes the different states in which the freq pin can be used. table 1 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor to sgnd dc voltage 50khz to 900khz any of the above external clock phase-locked to external clock figure 7. relationship between oscillator frequency and resistor value at the freq pin freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 7812 f07 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 minimum on- time considerations minimum on-time t on(min) is the smallest time duration that the ltc7812 is capable of turning on the top mosfet ( bottom mosfet for the boost controller ). it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t o n ( m i n ) _ b u c k < v o u t v i n ( f ) t o n ( m i n ) _ b o o s t < v o u t ? v i n v o u t ( f ) ltc7812 7812fc
29 for more information www.linear.com/ltc7812 applications information if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc7812 is approximately 95ns for the buck and 120ns for the boost. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. this is of particu - lar concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses , four main sources usually account for most of the losses in ltc7812 circuits : 1) ic v bias current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v bias current is the dc supply current given in the electrical characteristics table, which excludes mos - fet driver and control currents. v bias current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets . each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc from an output- derived source power through extv cc will scale the v in current required for the driver and control circuits by a factor of ( duty cycle)/ (efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis - tor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet . if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resis - tances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the top mosfet(s) (bot - tom mosfet for the boost), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7)v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that ltc7812 7812fc
30 for more information www.linear.com/ltc7812 applications information c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including diode conduction losses during dead- time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to di load(esr) , where esr is the effective series resistance of c out . di load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti - loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in figure 9 will provide an adequate starting point for most applications. the i th series r-c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca - pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response . the gain of the loop will be increased by increasing r and the bandwidth of the loop will be increased by decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. buck design example as a design example for the buck channel, assume v in = 12v (nominal) , v in = 22v (max) , v out = 3.3v, i max = 6a, v sense(max) = 50mv, and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the freq pin ltc7812 7812fc
31 for more information www.linear.com/ltc7812 applications information to gnd, generating 350khz operation. the minimum inductance for 30% ripple current is: d i l = v o u t ( f ) ( l ) 1 ? v o u t v i n ( n o m i n a l ) ? ? ? ? ? ? ? ? a 3.9h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 6.88a. increasing the ripple current will also help ensure that the minimum on-time of 95ns is not violated. the minimum on-time occurs at maximum v in : t o n ( m i n ) = v o u t v i n ( m a x ) ( f ) = 3.3 v 22 v ( 350 k h z ) = 429 ns the r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (43mv): r s e n s e 43 m v 6.88 a = 0.006 choosing 1% resistors: r a = 25k and r b = 80.6k yields an output voltage of 3.33v. the power dissipation on the top side mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p m a i n = 3.3 v 22 v ( 6 a ) 2 1 + ( 0.005 ) ( 50 c ? 25 c ) { } ( 0.035 ) + ( 22 v ) 2 6 a 2 ( 2.5 ) ( 215 pf ) ? 1 5 v ? 2.3 v + 1 2.3 v ? ? ? ? ? ? ( 350 k h z ) = 433m w a short- circuit to ground will result in a folded back cur - rent of: i s c = 20 m v 0.006 ? 1 2 95 ns ( 22 v ) 3.9 h ? ? ? ? ? ? = 3.07 a with a typical value of r ds(on) and z = (0.005/c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p s y n c = ( 2.23 a ) 2 ( 1.125 ) ( 0.022 ) = 233 m w which is less than under full-load conditions. the input capacitor to the buck regulator c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input volt - age. the output voltage ripple due to esr is approximately: v oripple = r esr (di l ) = 0.02(1.75a) = 35mv p-p pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. figure 8 illustrates the current waveforms present in the various branches of the synchronous boost and buck regulators operating in the continuous mode. check the following in your layout: 1. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the path formed by the top n-channel mosfet, bottom n-channel mosfet and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 2. do the ltc7812 v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. ltc7812 7812fc
32 for more information www.linear.com/ltc7812 4. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur - rent peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 5. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small- signal nodes, especially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc7812 and occupy minimum pc trace area. 6. use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pins of the ic. pc board layout debugging start with one controller on at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit . monitor the output switch - ing node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 25% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well- designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un - dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry , the regulator will still maintain control of the output voltage. applications information ltc7812 7812fc
33 for more information www.linear.com/ltc7812 applications information figure 8a. branch current waveforms for boost regulator figure 8b. branch current waveforms for buck regulator r l1 l1 sw1 r sense1 r in v in v out1 c out1 7812 f08a bold lines indicate high switching current. keep lines to a minimum length. v r l l sw r sense v out c out v in c in r in bold lines indicate high switching current. keep lines to a minimum length. 7812 08b ltc7812 7812fc
34 for more information www.linear.com/ltc7812 applications information compensation and v mid capacitance in a cascaded boost+buck regulator when using the ltc7812 as a cascaded boost+buck regulator, the boost and buck regulator control loops are compensated individually. while this may seem more complicated, this is actually advantageous, as the inher - ently fast buck loop can be designed to handle the output load transient, while the boost loop is less important and can be slower. the amount of capacitance needed on the intermediate v mid node (boost output) and the buck output v out depends on a number of factors, including the input voltage, output voltage, load current and the nature of any transients, and the mode of operation (burst mode operation, forced continuous mode, or pulse-skipping mode). in general, the buck regulator should be designed to handle any output load transients and provide sufficiently low output ripple. the boost regulator does not need to respond as fast, as the v mid node can tolerate relatively high ripple and/or transient dips and therefore does not necessarily need a lot of capacitance. the v mid node capacitance needs to be able to handle the input ripple current from the buck regulator. it also needs to be large enough that the boost regulators voltage ripple and/or transient dips do not ap - pear as significant input line steps to the buck regulator and feed through to the buck regulators output. the ripple on the v mid node is higher in burst mode opera - tion and pulse-skipping mode than in forced continuous mode, especially at light loads and/or if the input voltage is slightly below the regulated boost output (v mid ) volt - age. thus, burst mode and pulse-skipping mode generally require more v mid capacitance than in forced continuous mode to maintain a similar amount of ripple. the capacitance on the v mid node can be all ceramic, or some combination of ceramic and polarized (tantalum, electrolytic, etc.) capacitors. choosing the v mid voltage in a cascaded boost+buck regulator there are many performance tradeoffs when considering where to set the v mid (boost output) regulation voltage (v mid_reg ) relative to the input voltage (v in ) range and output (buck) regulation voltage (v out_reg ). these trade- offs include efficiency, quiescent current, switching noise/ emi, and voltage ripple. remember that v mid will follow v in if v in > v mid_reg ( see the boost controller operation when v in > v out section in the operation section.) if v in < v mid_reg , v mid is regulated to v mid_reg . consider as an example an automotive application that requires a regulated 12v output voltage generated from a vehicle battery . the battery spends most of its operating lifetime in a normal range of 10v to 16v, but may dip to as low as 2.5v during engine start and rise as high as 38v during high voltage transients. we can designate the minimum normal operating voltage as v in_min_op = 10v, and the maximum normal operating voltage as v in_max_op = 16v. so what voltage should we choose for v mid_reg ? regulated output voltage in this example, note that we want a tightly regulated output (v out_reg = 12v), which is within our normal operating range (v in_min_op < v out_reg < v in_max_op ). we want v mid_reg > v out_reg to provide headroom for the buck regulator, but we have a choice of whether to set v mid_reg above or below v in_max_op . option a : v mid_ reg > v out_ reg and v mid_ reg > v in_max_op in this option, we set v mid_ reg > v in_ max_ op ( e . g ., v mid_reg = 18v). both the boost regulator and the buck regulator are switching (at full, constant frequency if in forced continuous mode) over the full 10v to 16v nor - mal operating range. since the boost regulator is always ltc7812 7812fc
35 for more information www.linear.com/ltc7812 applications information switching, the efficiency is lower and the input ripple and emi, while predictable and still low, are higher than other potential options. option b : v in _ min _ op < v out _ reg < v mid _ reg < v in_max_op this is similar to option a, but v mid_reg is set within the normal operating input voltage range (e.g., v mid_reg = 14v). when v in is well below v mid_reg , this option is like option a. but as v in approaches v mid_reg , the boost controller will gradually begin skipping cycles (even in forced continuous mode) once it reaches minimum-on- time. if v in > v mid_reg , then v mid follows v in . in this region, option b is more efficient than option a since the boost is not switching. but this is at the expense of the cycle-skipping (non-constant frequency ripple) when v in is slightly below v mid_reg . loosely regulated output (pass-through regulator) in some applications, it is not critical that v out be tightly regulated, but rather that it remains within a certain voltage range. suppose, in our example, that it is only important that v out be maintained within the normal battery operating voltage range of 10v to 16v . we can consider a third option: option c: v mid_reg = v in_min_op and v out_reg = v in_max_op here we set v mid_reg = v in_min_op = 10v and v out_reg = v in_max_op =16v. so the boost regulator only boosts when v in < 10v and the buck regulator only bucks when v in >16v. when v in is between 10v to 16v, the circuit is in a pass-through or wire mode where there is very little switching. the boost regulator is not boosting (tg2 is on 100% in forced continuous mode) and the buck regulator is operating in dropout (with tg1 on at an effective 99%duty cycle.) this makes the circuit very efficient, especially at heavy loads, with extremely low input and output ripple and emi. note that in this pass-through mode, the circuit does not benefit from the ltc7812s ultralow quiescent current of 33a in burst mode since the buck regulator does not go to sleep because v out < v out_reg = 16v. regulated output voltage below normal input voltage operating range in some applications, the desired output voltage might be less than the minimum normal operating voltage, but still higher than the worst-case minimum input voltage. consider our previous example, but instead suppose we want v out = 5v. in this case, we can set our v mid_reg such that: option d: v in_min_op > v mid_reg > v out_reg so we might set v mid_reg just below 10v, so that the boost regulator never switches within the normal operating range and only needs to boost during the input voltage dips below 10v. the buck controller always regulates the v out to 5v, and the boost regulators inductor and v mid capacitance create a filter that substantially reduces any input ripple and results in very little conducted emi on the input. table 1 summarizes some of the performance trade-offs of these four potential ways to set the v mid regulation voltage in an ltc7812 cascaded boost+buck regulator. ltc7812 7812fc
36 for more information www.linear.com/ltc7812 applications information table 1. summary of trade-offs in determining the v mid voltage in a cascaded boost+buck regulator a b c d option v mid_reg > v out_reg and v mid_reg > v in_max_op v in_min_op < v out_reg < v mid_reg < v in_max_op v mid_reg = v in_min_op and v out_reg = v in_max_op (pass-through /wire mode) v in_min_op > v mid_reg > v out_reg example for normal input operating range of 10v C 16v (v in_min_op = 10v v in_max_op = 16) with a full range of 2.5v C 38v v mid_reg = 18v v out = v out_reg = 12v v mid_reg =14v v out = v out_reg = 12v v mid_reg = 10v v out_reg = 16v v out = 10v C 16v v mid_reg = 10v v out = v out_reg = 5v boost boosting in normal operating range? yes , over full range yes, when v in < v mid_reg no no buck bucking in normal operating range? yes , over full range yes , over full range no, in dropout yes , over full range ltc7812 no-load quiescent current in burst mode operation 33a 33a ~3ma 33a heavy load efficiency slightly lower high when not boosting; slightly lower when boosting highest high input ripple low low when boosting; very low when not boosting; some cycle-skipping during transition extremely low very low output ripple low low extremely low low emi in normal operating range low very low when not boosting; low when boosting extremely low very low example for normal operating range: v in_min_op = 10v C v in_max_op = 16v v mid_reg = 18v v out = v out_reg = 12v figure 10 v mid_reg =14v v out = v out_reg = 12v figure 9 v mid_reg = 10v v out_reg = 16v v out = 10v C 16v figure 11 v mid_reg = 10v v out = v out_reg = 5v figure 12 ltc7812 7812fc
37 for more information www.linear.com/ltc7812 figure 9. wide input range to 12v/8a low i q , cascaded boost+buck regulator (v mid boosted to 14v) + + + typical applications ltc7812 7812fc c b1 0 .1f 50 amplitude (dbv) v out 12v 8a* v mid , 14v** r sense2 2m r sense1 3m l2, 1h m bot2 m top2 m top1 m bot1 v in 5v to 38v down to 2.5v after start-up l1, 4.7h r b1 499k r a1 35.7k freq intv cc v fb2 run1 4.75k 4.7nf c ss2 0.01f c in1 33f c ss1 0.1f 100pf extv cc pgood1 ov2 ss2 i th1 sgnd 7812 f09a run2 c in2,3 6.8f i th2 sense2 ? sense2 + v fb1 pgnd v bias tg2 sw2 boost2 bg2 c b2 0.1f bg1 boost1 sw1 tg1 sense1 + sense1 ? pllin/mode track/ss1 ltc7812 1k 1000pf 6.8nf 820pf c mid1,2,3,4 6.8f c out3 47f c out1,2 22f c mid5 33f r b2 499k r a2 46.4k m top1 , m top2 , m bot1 , m bot2 : infineon bsc027n04ls l1: wurth 7443320470 4.7f l2: wurth 7443320100 c in1, c mid5 : kemet t521x336m050ate075 c out3 : kemet t521v476m020ate055 d b1 , d b2 : central semi cmdsh-4e *when v in < 8v, maximum load current available is reduced **v mid = 14v when v in < 14v v mid follows v in when v in > 14v 1m 1m intv cc d b1 pgood1 ov2 cispr-25 conducted emi measurement v in = 13.5v, i out = 8a 0 0 30 15 frequency (mhz) 100 50 d b2 amplitude (dbv) 7812 f09b 7812 f09c cispr-25 conducted emi measurement with additional input filter (l = 240nh, c = 33f) v in = 13.5v, i out = 8a 0 0 30 15 frequency (mhz) 100
38 for more information www.linear.com/ltc7812 figure 10. wide input range to 12v/8a low i q , cascaded boost+buck regulator (v mid = 18v) + + + typical applications ltc7812 7812fc c b1 0 .1f v out 12v 8a* v mid , 18v** r sense2 2m r sense1 3m l2, 1h m bot2 m top2 m top1 m bot1 v in 5v to 38v down to 2.5v after start-up l1, 4.7h r b1 499k r a1 35.7k freq intv cc v fb2 run1 4.75k 4.7nf c ss2 0.01f c in1 33f c ss1 0.1f 100pf extv cc pgood1 ov2 ss2 i th1 sgnd 7812 f10 run2 1000pf i th2 sense2 ? sense2 + v fb1 pgnd v bias tg2 sw2 boost2 bg2 c in2,3 6.8f bg1 boost1 sw1 tg1 sense1 + sense1 ? pllin/mode track/ss1 ltc7812 1k c b2 0.1f 6.8nf 820pf c mid1,2,3,4 6.8f c out3 47f c out1,2 22f c mid5 33f r b2 499k r a2 35.7k 1m 1m 4.7f intv cc pgood1 ov2 m top1 , m top2 , m bot1 , m bot2 : infineon bsc027n04ls l1: wurth 7443320470 l2: wurth 7443320100 c in1 , c mid5 : kemet t521x336m050ate075 c out3 : kemet t521v476m020ate055 d b1 , d b2 : central semi cmdsh-4e *when v in < 8v, maximum load current available is reduced d b1 **v mid = 16v when v in < 16v v mid follows v in when v in > 16v d b2
39 for more information www.linear.com/ltc7812 typical applications figure 11. wide input range pass-through cascaded boost+buck regulator + + + ltc7812 7812fc c b1 0 .1f v out 10v to 16v* 8a** v mid , 10v*** r sense2 2m r sense1 3m l2, 1h m bot2 m top2 m top1 m bot1 v in 5v to 38v down to 2.5v after start-up l1, 4.7h r b1 499k r a1 26.1k freq intv cc v fb2 run1 4.75k 4.7nf c ss2 0.01f c in1 33f c ss1 0.1f 100pf extv cc pgood1 ov2 ss2 i th1 sgnd 7812 f11a run2 c in2,3 6.8f i th2 sense2 ? sense2 + v fb1 pgnd v bias tg2 sw2 boost2 bg2 1000pf bg1 boost1 sw1 tg1 sense1 + sense1 ? pllin/mode track/ss1 ltc7812 1k c b2 0.1f 6.8nf 820pf c mid1,2,3,4 6.8f c out3 47f c out1,2 22f c mid5 33f r b2 499k r a2 68.1k 1m 1m 4.7f intv cc pgood1 ov2 m top1 , m top2 , m bot1 , m bot2 : infineon bsc027n04ls l1: wurth 7443320470 l2: wurth 7443320100 c in1 , c mid5 : kemet t521x336m050ate075 c out3 : kemet t521v476m020ate055 d b1 , d b2 : central semi cmdsh-4e **when v in < 8v, maximum load current available is reduced d b1 ***v mid = 10v when v in < 10v v mid follows v in when v in > 10v *v out = 10v when v in < 10v v out = 16v when v in > 16v v out follows v in when v in is 10v to 16v 7812 f11b cispr-25 conducted emi measurement v in = 13.5v, i out = 8a 0 0 30 d b2 15 frequency (mhz) 100 50 amplitude (dbv)
40 for more information www.linear.com/ltc7812 typical applications figure 12. wide input range to 5v/5a low i q cascaded boost + buck regulator (v mid boosted to 10v) + + + ltc7812 7812fc v out 5v 5a v mid , 10v* r sense2 2m r sense1 6m l2, 1.2h m bot2 m top2 m top1 m bot1 l1, 4.9h v in 5v to 38v down to 2.5v after start-up r b1 375k r a1 68.1k freq intv cc v fb2 run1 15k 1.5nf c ss2 0.01f c ss1 0.1f c in1 220f 100pf extv cc pgood1 ov2 ss2 i th1 sgnd 7812 f12a run2 i th2 1000pf sense2 ? sense2 + v fb1 pgnd v bias tg2 sw2 boost2 bg2 bg1 c b2 0.1f boost1 sw1 tg1 sense1 + sense1 ? pllin/mode track/ss1 ltc7812 3.6k 10nf 4.7f 820pf c out1 220f c mid1 220f r b2 499k r a2 68.1k 1m 1m intv cc pgood1 ov2 d b1 m top1 , m bot1 : infineon bsz097n04ls m top2 , m bot2 : infineon bsc027n04ls l1: wurth 744314490 l2: wurth 744325120 c in1 , c mid1 : suncon 50ce220lx c out1 : sanyo 6tpb220ml d b1 , d b2 : central semi cmdsh-4e *v mid = 10v when v in < 10v v mid follows v in when v in > 10v 7812 f12b d b2 cispr-25 conducted emi measurement v in = 13.5v, i out = 8a 0 0 30 15 frequency (mhz) 100 50 amplitude (dbv) c b1 0 .1f
41 for more information www.linear.com/ltc7812 typical applications figure 13. high efficiency, 5v to 24v, v in to 24v/5a and 3.3v/5a dc/dc regulator + + + ltc7812 7812fc c b1 , 0 .1f 4.7f r sense1 6m l2, 3.5h l1 3.3h 4m r sense2 m bot2 m top2 r a1 68.1k r b1 215k c out7 220f v out1 3.3v 5a 7812 f13 c out3,4,5,6 22f m top1 , m bot1 : infineon bsz097n04ls m top2 , m bot2 : infineon bsc027n04ls l1: wurth 744325330 l2: wurth 7443556350 c in1 : kemet t521x336m050ate075 c out2 : kemet t520b157m004ate015 c out7 : suncon 50ce220lx v out2 24v 5a* d b1 , d b2 : central semi cmdsh-4e *when v in < 8v, maximum load current available is reduced pins not used in this circuit: run1, run2 c in1 33f c in2,3 6.8f c out2 150f c out1 100f v in 5v to 24v m top1 m bot1 c7 1000pf ltc7812 freq pllin/mode extv cc pgood1 ov2 ss2 sgnd i th2 track/ss1 c b2 , 0.1f i th1 15k 820pf c ss2 , 0.1f c ss1 , 0.1f 150pf ov2 8.66k 15nf 220pf r b2 232k 1m 1m intv cc pgood1 intv cc v fb2 sense2 ? sense2 + v fb1 pgnd r a2 12.1k v bias tg2 sw2 boost2 bg2 bg1 boost1 sw1 tg1 sense1 + d b2 sense1 ? d b1
42 for more information www.linear.com/ltc7812 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) package description please refer to http://www .linear.com/product/ltc7812#packaging for the most recent package drawings. ltc7812 7812fc
43 for more information www.linear.com/ltc7812 revision history rev date description page number a 06/16 changed graph, efficiency vs load current, v in = 18v corrected figure 13 6 41 b 04/17 changed v fb1 and v fb2 to v fb1 corrected p main equation added v mid = 18v 4 31 38 c 05/17 changed reference voltage line regulation condition 3 ltc7812 7812fc
44 for more information www.linear.com/ltc7812 ? linear technology corporation 2015 lt 0517 rev c ? printed in usa www.linear.com/ltc7812 related parts typical application part number description comments ltm4609 36v in , 34v out , buck-boost module regulator 4.5v v in 36v, 0.8v v out 34v, up to 4a, 15mm 15mm lga and bga packages ltm8056 58v in , 48v out , buck-boost module regulator 5v v in 58v, 1.2v v out 48v, up to 5.4a, 15mm 15mm 4.92mm bga package ltc3789 high efficiency synchronous 4-switch buck-boost controller 4v v in 38v, 0.8v v out 38v, 4mm 5mm qfn-28, ssop-28 LT3790 60v 4-switch synchronous buck-boost controller 4.7v v in 60v, 1.2v v out 60v, tssop-38 lt8705 80v v in and v out synchronous 4-switch buck-boost dc/dc controller 2.8v v in 80v, 1.3v v out 80v, regulates v out , i out , v in , i in , 5mm 7mm qfn-38, modified tssop package for high voltage ltc3786 low i q synchronous step-up dc/dc controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, i q = 55a pll fixed frequency 50khz to 900khz, 3mm 3mm qfn-16, msop-16e ltc3787 low i q , multiphase, dual channel single output synchronous step-up dc/dc controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, pll fixed frequency 50khz to 900khz, i q = 135a ltc 3891 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3899 60v, triple output, buck/buck/boost synchronous controller with 29a burst mode i q 4.5v (down to 2.2v after start-up) v in 60v, v out up to 60v, buck v out range: 0.8v to 60v, boost v out up to 60v ltc3859al 38v, low i q , triple output, buck/buck/boost synchronous controller with 28a burst mode i q 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, buck v out range: 0.8v to 24v, boost v out up to 60v ltc3892/ ltc3892-1 60v low i q , dual, 2-phase synchronous step-down dc/dc controller with 29a burst mode i q 4.5v v in 60v, 0.8v v out 0.99v in , 5mm 5mm qfn-32, tssop-28 packages low emi, wide input range pass-through cascaded boost+buck regulator + + + ltc7812 7812fc c b1 0 .1f v out 10v to 16v* 8a** v mid , 10v*** r sense2 2m r sense1 3m l2, 1h m bot2 m top2 m top1 m bot1 v in 5v to 38v down to 2.5v after start-up l1, 4.7h r b1 499k r a1 26.1k freq intv cc v fb2 run1 4.75k 4.7nf c ss2 0.01f c in1 33f c ss1 0.1f 100pf extv cc pgood1 ov2 ss2 i th1 sgnd 7812 ta02 run2 c in2,3 6.8f i th2 sense2 ? sense2 + v fb1 pgnd v bias tg2 sw2 boost2 bg2 1000pf bg1 boost1 sw1 tg1 sense1 + sense1 ? pllin/mode track/ss1 ltc7812 1k c b2 0.1f 6.8nf 820pf c mid1,2,3,4 6.8f c out3 47f c out1,2 22f c mid5 33f r b2 499k r a2 68.1k 1m 1m 4.7f intv cc pgood1 ov2 m top1 , m top2 , m bot1 , m bot2 : infineon bsc027n04ls l1: wurth 7443320470 l2: wurth 7443320100 c in1 , c mid5 : kemet t521x336m050ate075 c out3 : kemet t521v476m020ate055 d b1 , d b2 : central semi cmdsh-4e **when v in < 8v, maximum load current available is reduced d b1 ***v mid = 10v when v in < 10v v mid follows v in when v in > 10v *v out = 10v when v in < 10v v out = 16v when v in > 16v v out follows v in when v in is 10v to 16v d b2

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